1. Field of the Invention
The present invention relates to the CMOS process, and more particularly to the design algorithm of the CMOS process.
2. Description of the Prior Art
The CMOS (Complementary Metal Oxide Semiconductor) circuit design has the advantage of low power compared with the BJT (Bipolar Junction Transistor), but has suffered from performance limitations. Because high speed digital design is requisite and designs with a gate count of more than ten millions are on the horizon, the process down sizing to 0.18 um/0.13 um or smaller scale is the trend for performance. However, the static and dynamic current consumption will increase rapidly due to faster devices. From the point of view of reducing power, the operation voltage is made as low as possible and the device threshold voltage is as large as possible. This, however, reduces the IC performance. Reducing the threshold voltage or increasing the saturation current will improve the delay time of the device. In other words, the device will transition from one stage to the other stage more quickly. However, this method will increase the switching current and reduce the noise margin, meaning that the power consumption will become larger.
In FIG. 1, a basic MOS structure is formed on a semiconductor substrate 10. The MOS structure includes a gate 12, a gate oxide 14, spacers 16, offset spacers 18, pocket regions 20, HDD regions 22 and source/drain regions 24.
A conventional pocket implant process is shown in FIG. 2. In FIG. 2, two MOS devices are formed on a semiconductor substrate 50 and isolated by a shallow trench isolation 52. Each device includes a gate 56, a gate oxide 58 and a well region 54. The conventional pocket implant process with a normal dose density is performed to a predefined region of each device by covering other regions with a photoresistor 60.
Obtaining both reduction of power consumption and good performance will inevitably increase the price of the product. Thus, an algorithm that both obtains power and performance enhancement and prevents too many changes to the process recipes in CMOS design needs to be developed.
The object of the present invention is to solve the above-mentioned problems and to provide a method for multi-threshold voltage CMOS process optimization.
The present invention achieves the above-indicated object by providing a method for multi-threshold voltage CMOS process optimization comprising the steps of: providing a semiconductor substrate with a plurality of devices of different threshold voltages; establishing a plurality of types of timing models for a timing calculation, based on the plurality of devices of different threshold voltages; obtaining a static timing analysis (STA) report through the timing calculation; defining a large and a small setup time margin as a Tl and a Ts, based on the static timing analysis report; changing the devices whose setup time margin are less than Ts to low threshold devices and changing the devices whose setup time margin are greater than Tl to high threshold devices, such that an enhanced static timing analysis report is obtained; performing a first pocket implant process for the low threshold devices with a first dose density by covering the high threshold devices; performing a second pocket implant process for the high threshold devices with a second dose density, greater than the first dose density, by covering the low threshold devices.